The present invention relates to a phase change memory device and a manufacturing method thereof, and more particularly to a phase change memory device capable of ensuring a sensing margin, and a manufacturing method thereof.
Memory devices may be categorized into a Random Access Memory (RAM) or a Read Only Memory (ROM) device. RAM devices are volatile memory devices (such as Dynamic RAM, i.e., DRAM, and Static RAM, i.e., SRAM), which will lose input information when power is off. The ROM devices are non-volatile memory devices (such as flash memory and Electrically Erasable Programmable ROM, i.e., EEPROM), which preserves the stored state of input information even when power is off.
Although DRAMs are considered very good memory devices, there are known difficulties for high integration as each DRAM requires a high charge storage capacity leading to increased electrode surface area. High integration is also considered to be difficult for flash memories as each flash memory having a laminated structure of two gates requires an operational voltage higher than its power source voltage and thus requires a separate booster circuit in order to establish the voltage necessary for write and erase operations.
Thus, studies were made to develop a new type of highly integratable non-volatile memory device having a simple and not unduly complicated structure. A phase change memory (in particular, a phase change RAM) is one such non-volatile memory device being researched.
A phase change memory device is a memory device in which the current flow between upper and lower electrodes causes the phase change layer interposed between the electrodes to undergo a phase change between a crystalline phase and an amorphous phase. The resistance difference of the phase change of the phase change layer is then used to discern the types of information stored in the memory cell. More specifically, the phase change memory device uses a Chalcogenide layer, a compound layer of Germanium (Ge), Stibium (Sb) and Tellurium (Te), as the phase change layer. Joule heat generated through the application of a current causes the Chalcogenide layer to undergo a phase change between a crystalline phase and an amorphous phase. Here, because the phase change layer has a higher resistance when in the amorphous phase as compared to the crystalline phase, the phase change memory uses a read mode to distinguish whether the information stored in the phase change memory cell corresponds to logic “1” or logic “0” by detecting the current flowing through the phase change layer.
In such a phase change memory device, the laminated pattern of the phase change layer and the upper electrode is formed within the unit phase change cell. The small size of the phase change layer results in changes in the composition of the phase change layer caused by an etching loss and so forth.
A proposed solution to this problem is a structure in which, as illustrated in FIG. 1, a phase change layer 130 and an upper electrode 132 are formed across two adjoining phase change cells. In such a structure, the phase change layer 130 is larger while each side edge of the phase change layer 130 is removed with respect to the two adjoining phase change cells. Thus, as compared to a structure in which each phase change cell is formed with a phase change layer, the afore-described memory device reduces etching losses, thereby avoiding changes at the edges of a phase change layer.
In FIG. 1, the reference numerals 100, 102, 110, 112, 118, 120, 122, 124, 134, 140 designate the following: a semiconductor substrate 100; an active area 102; a word line 110, 112; a contact plug 118; a lower electrode 120; a common source line 122; a lower electrode contact plug 124; an upper electrode contact plug 134; and a bit line 140.
The conventional phase change memory device having the above-described structure decreases the amount of variation in the current required for the phase change of a phase change layer by reducing the etching loss of the phase change layer; however, the phase change memory device suffers from characteristic deterioration because an undesired thermal phase change occurs between two adjoining phase change cells directed toward the bit line, specifically, two phase change cells across which one phase change layer is arranged. Such an undesired phase change is referred to as “thermal cross-talk”. For example, thermal cross-talk changes stored data or negatively influences the phase change cell, thereby causing a sensing margin decrease in the sense amp. As a result, despite the reduction in the phase change layer's etching loss, the thermal cross-talk causes the deterioration of the above-mentioned conventional phase change memory device's desired characteristics.